The present disclosure relates to methods for generating test patterns for semiconductor integrated circuits, and more particularly to generation of a test pattern for use in a test on a CMOS synchronization semiconductor integrated circuit subjected to scan design.
Semiconductor integrated circuits as final products are not always non-defective, and include defective products with a stuck-at fault in which the value of a signal line is stuck at 0 or 1. In view of this, a product test for detecting a stuck-at fault needs to be conducted on all the signal lines of a semiconductor integrated circuit before shipment. In addition, with recently advanced process miniaturization, it is also necessary to detect not only a stuck-at fault but also a delay fault, i.e., to determine whether a change in value of a signal line is transmitted within a specified time or not. Thus, a test on a semiconductor integrated circuit is an important item for evaluations of performance and reliability. In some cases, a test cost occupies a half of the total cost for design and manufacturing.
Scan design is a technique for making a test on a semiconductor integrated circuit easier. A test on a semiconductor integrated circuit subjected to scan design is performed in the following manner. First, a test pattern is set in scan flip-flops by scan-in, and then is applied to a combinational circuit to capture a test response in the scan flip-flops. Scan-out of the captured test response is performed simultaneously with scan-in of the next test pattern.
A change in the value of a scan flip-flop causes changes in the values of not only transistors constituting the scan flip-flop but also transistors of a combinational circuit which receives an output of the scan flip-flop. Accordingly, a large amount of power is consumed in a semiconductor integrated circuit, thereby increasing the circuit temperature. In particular, the percentage of scan flip-flops which operate at the same time, i.e., change their values at the same time, is about 20% at most in normal operation, but rises to about 50% during a test. Accordingly, heat generation during the test is larger than that in the normal operation. Since operation speed of a CMOS transistor depends on the temperature, it is essential to control the circuit temperature during a test in order to obtain a highly accurate test result.
A test pattern sequence for a scan test can be automatically generated by an automatic test pattern generation (ATPG) tool. A test pattern sequence generated in designing a semiconductor integrated circuit is used for, for example, a manufacturing test before shipment or a field test after shipment. In general, a test pattern sequence generated by an ATPG tool includes a don't care bit, and power consumption of a semiconductor integrated circuit during a test, and eventually the temperature thereof, greatly change depending on the way of determining a don't care value and the order of applying test patterns. There is a known test pattern generation method for a low power consumption test for reducing peak power consumption and average power consumption of a semiconductor integrated circuit during the test and a low heat generation test for reducing heat generation of the semiconductor integrated circuit during the test. There is also a known test pattern generation method for a power consumption uniformizing test for reducing a change in power consumption of a semiconductor integrated circuit during the test (see, for example, Sudarshan Bahukudumbi, Krishnendu Chakrabarty, “Power Management for Wafer-Level Test During Burn-In,” ats, pp. 231-236, 2008 17th Asian Test Symposium, 2008).
A semiconductor integrated circuit to which a test pattern is applied is not uniformly activated in its entire region, but is divided into one or more regions, each of which is activated to be at a high temperature, and one or more regions, each of which is not activated. Power consumption in the activated regions varies according to an applied test pattern. With further systematization and increase in scale of semiconductor integrated circuits in future, variation in spatial temperature of a semiconductor integrated circuit during a test is expected to be more conspicuous. This might be a serious problem for tests on semiconductor integrated circuits in progress of enhancing the speed and miniaturization.
Some known techniques were intended to control the temperature of a semiconductor integrated circuit from outside the circuit. However, this control requires an additional device, and thus, is not efficient. In addition, to uniformize the circuit temperature to enhance the test accuracy, mere uniformization of power consumption is insufficient, and spatial and temporal variations in power consumption needs to be considered.
There is also another known technique which is intended to reduce a temporal variation in power consumption of the entire circuit. However, this conventional technique does not consider a spatial variation in power consumption in the circuit and spatial and temporal variations in circuit temperature, and does not sufficiently satisfy a detailed test required for recent semiconductor integrated circuits.
Accordingly, there is a need for a test pattern generation method which can spatially and temporally uniformize the temperature of a semiconductor integrated circuit by devising a test pattern without an additional device.